In a system for transmitting a digital signal using a direct sequence spread spectrum, the “0” and “1” bits are encoded with respective symbols sent by the transmitter, and decoded at the receiver by a finite impulse response (FIR) filter.
In the case where the bits are encoded using a spreading code of length N, the symbols encoding the “0” and “1” bits are each in the form of a series of N symbol elements (“0” or “1”), called “chips”, distributed over either of two different levels and transmitted at a predetermined fixed frequency F.
The N symbol elements encoding the “1” bit are anti-correlated to the corresponding N symbol elements encoding the “0” bit, i.e., the symbol elements of the same rank within both of these two symbols have opposite values.
For example, if and when a symbol element of the symbol encoding the “1” bit is at level 1, the corresponding symbol element of the symbol encoding the “0” bit is at level −1. In the same way, if and when a symbol element of the symbol encoding the “1” bit is at level −1, the corresponding symbol element of the symbol encoding the “0” bit is at level 1.
The spread binary message is then used to phase-modulate the carrier, appearing in the form of a time-dependent sine wave recorded as p(t)=cos(2Πfp.t+φ), where fp is its frequency and φ its original phase.
FIG. 1 shows the architecture of a BPSK synchronous receiver chain. This architecture conventionally leads to interfacing analog radio modules with a digital processing system working at a near-zero frequency. The information processing is then carried out at this frequency, which advantageously makes it possible to use analog-to-digital converters working at lower frequencies. In this way, when the digital signal reaches the receiver, it is captured by an antenna 10, and then transmitted to the analog unit of the chain, comprising the low-noise amplifier 20 (LNA), the local oscillator 31 as well as the mixer 30. Since the operation of these elements is not modified within the framework of the subsequently described embodiments of the invention, these elements will not be described in greater detail.
It will simply be noted that the mixer 30, receiving at its first input the signal from the output of the amplifier LNA, receives at its second input, connected to the local oscillator 31, a frequency corresponding to the carrier frequency of the signal. This has the effect of bringing the signal back to baseband. Thus, at the output of the mixer, there is a binary message in continuous baseband form, added to a high-frequency component centered over twice the carrier frequency. As a matter of fact, this demodulation operation reveals the spectral motif of the baseband signal, but also a motif at twice the demodulation frequency, i.e., at about the frequency 2 fp.
A low pass filtering stage 40 at the output of the mixer 30 makes it possible to eliminate the harmonic distortion due to spectral redundancy during demodulation of the signal. In order to accomplish this, the low pass filter 40 has a cut-off frequency equal to the maximum frequency of the spread baseband message, which means that only the baseband message is found at its output, i.e., brought back to approximately zero frequency.
The resulting signal is then digitized by the analog-to-digital converter (ADC) 50. It is sampled at a sampling frequency respecting Shannon's limit. In other words, the sampling frequency is assumed to be equal to at least twice the maximum frequency presented by the spectral power density of the spread baseband message.
At the output of the ADC, the DSSS decoder comprises a matched filter stage 60, making it possible to recover the synchronization of the signal being decoded with respect to the wanted information. More precisely, this is a finite impulse response (FIR) filter, characterized by its impulse response coefficients {ai}i-0, 1, . . . , n. The matched filter-based decoding process consists in matching the series of coefficients ai to the exact replica of the spreading code selected. For example, if the Barker code 7 (−1−1−1 1 1−1 1) was used, the coefficients of the matched filter are −1−1−1 1 1−1 1.
The structure of the matched filter 60, described in FIG. 2, is that of a shift register REG receiving each sample of the input signal IN. The filter is synchronized to the same sampling frequency as that of the incoming signal. The shift register includes N bistable circuits in the case of symbols with N symbol elements, which cooperate with a combinational circuit COMB, designed in a manner known by those skilled in the art and involving the series of coefficients ai such that the output signal OUT produced by the filter has an amplitude directly dependent upon the level of correlation observed between the sequence of the N last samples captured by this filter and the series of the N symbol elements of one of the two symbols, e.g., the series of the N elements of the symbol encoding a “1” bit of the digital signal.
Thus, the matched filtering operation comprises matching the series of coefficients ai to the exact replica of the selected spreading code, in order to correlate the levels of the symbol elements that it receives in succession at its input to the levels of the successive symbol elements of one of the two symbols encoding the “0” and “1” bits, e.g., the symbol elements of the symbol encoding the “1” bit.
The output of the finite response filter 60 typically supplies synchronization peaks, whose sign provides the bit value of the original message at that moment: if the peak is negative, said value is a “0”, and a “1” if the peak is positive. In order to transform the symbols thus decoded into a binary data flow corresponding to the original message and to associate them with synchronization clock, these peaks are passed through hysteresis comparators, Comp1 and Comp2, respectively. The original message as well as the synchronization clock are then restored at the output of the hysteresis comparators.
More precisely, the first comparator Comp1 toggles as soon as the signal passes below a lower threshold value or above an upper threshold value, and then supplies a one-bit digital signal corresponding to the data. The second comparator toggles as soon as the signal passes above or below the lower threshold value, and then supplies a one-bit digital signal which serves as a capture clock for the data. The lower and upper threshold values are adjustable.
However, when the transmission channel is noisy, a significant degradation in the performance of the matched filter-based decoding process DSSS may be observed and, most often, when the wanted signal and the transmission channel noise are not completely decorrelated. In this context, errors may occur, both with respect to the restored binary message and the synchronization clock. Thus, a deterioration in the performance of the matched filter may be observed and, as a result, a significant increase in the bit error rate at the output of the decoding process, along with the reduction in the signal-to-noise ratio.
In order to attempt to improve the performance of the receiver device as it was just described, when in the presence of a noisy transmission channel, various solutions might be anticipated. In particular, it might be anticipated to increase the power of the signal upon transmission, which, however, involves a consequential increase in the electrical power consumed by the circuit. It might also be anticipated to use larger spectrum-spreading codes, but this might be detrimental to the speed, which would thereby be greatly reduced. Consequently, none of these solutions are satisfactory.